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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad5303/ad5313/ad5323 * 2.5 v to 5.5 v, 230 a, dual rail-to-rail voltage output 8-/10-/12-bit dacs * protected by u.s. patent no. 5684481; other patents pending. features ad5303: 2 buffered 8-bit dacs in 1 package a version: 1 lsb inl, b version: 0.5 lsb inl ad5313: 2 buffered 10-bit dacs in 1 package a version: 4 lsb inl, b version: 2 lsb inl ad5323: 2 buffered 12-bit dacs in 1 package a version: 16 lsb inl, b version: 8 lsb inl 16-lead tssop package micropower operation: 300 a @ 5 v (including reference current) power-down to 200 na @ 5 v, 50 na @ 3 v 2.5 v to 5.5 v power supply double-buffered input logic guaranteed monotonic by design over all codes buffered/unbuffered reference input options output range: 0 v to v ref or 0 v to 2 v ref power-on-reset to 0 v sdo daisy-chaining option simultaneous update of dac outputs via ldac pin asynchronous clr facility low power serial interface with schmitt-triggered inputs on-chip rail-to-rail output buffer amplifiers applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram buffer power-down logic resistor network string dac ad5303/ad5313/ad5323 v out a v out b v dd v ref a v ref b dac register dac register > sync sclk din gnd buf a sdo clr buf b string dac dcen ldac power-on reset pd buffer gain-select logic resistor network input register input register interface logic general description the ad5303/ad5313/ad5323 are dual 8-, 10-, and 12-bit buffered voltage output dacs in a 16-lead tssop package that operate from a single 2.5 v to 5.5 v supply consuming 230 a at 3v . their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 v/ s. the ad5303/ad5313/ ad5323 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with standard spi ? , qspi ? , microwire ? , and dsp interface standards. the references for the two dacs are derived from two reference pins (one per dac). these reference inputs may be configured as buffered or unbuffered inputs. the parts incorporate a power-on reset circuit, which ensures that the dac outputs power-up to 0v and remain there until a valid write to the device takes place. there is also an asynchronous active low clr pin that clears both dacs to 0 v. the outputs of both dacs may be updated simultaneously using the asynchronous ldac input. the parts contain a power-down feature that reduces the current consump- tion of the devices to 200 na at 5 v (50 na at 3 v) and provides software-selectable output loads while in power-down mode. the parts may also be used in daisy-chaining applications using the sdo pin. the low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. the power consumption is 1.5 mw at 5 v, 0.7 mw at 3 v, reducing to 1 w in power-down mode.
rev. a e2e ad5303/ad5313/ad5323especifications (v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted.) a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments dc performance 3, 4 ad5303 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.5 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5313 resolution 10 10 bits relative accuracy 0.5 4 0.5 2 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5323 resolution 12 12 bits relative accuracy 2 16 2 8 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 0.4 3% of fsr see figures 3 and 4 gain error 0.15 1 0.15 1% of fsr see figures 3 and 4 lower deadband 10 60 10 60 mv see figures 3 and 4 offset error drift 5 ? 12 ? 12 ppm of fsr/ c gain error drift 5 ? 5 ? 5 ppm of fsr/ c power supply rejection ratio 5 ? 60 ? 60 db
rev. a ad5303/ad5313/ad5323 e3e ac characteristics 1 a, b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5303 6 8 s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5313 7 9 s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5323 8 10 s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/ s major-code transition glitch energy 12 nv-s 1 lsb change around major carry (011 . . . 11 to 100 . . . 00) digital feedthrough 0.10 nv-s analog crosstalk 0.01 nv-s dac-to-dac crosstalk 0.01 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p, unbuffered mode total harmonic distortion ? 70 db v ref = 2.5 v 0.1 v p-p, frequency = 10 khz notes 1 guaranteed by design and characterization, not production tested. 2 see terminology section. 3 temperature range: a, b version: ? 40 c to +105 c. specifications subject to change without notice. (v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted.) timing characteristics 1, 2, 3 (v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted.) limit at t min , t max parameter (a, b version) unit conditions/comments t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 0 ns min sync to sclk rising edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 100 ns min minimum sync high time t 9 20 ns min ldac pulsewidth t 10 20 ns min sclk falling edge to ldac rising edge t 11 20 ns min clr pulsewidth t 12 4, 5 5 ns min sclk falling edge to sdo invalid t 13 4, 5 20 ns max sclk falling edge to sdo valid t 14 5 0 ns min sclk falling edge to sync rising edge t 15 5 10 ns min sync rising edge to sclk rising edge notes 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figures 1 and 2. 4 these are measured with the load circuit of figure 1. 5 daisy-chain mode only. (see figure 23.) specifications subject to change without notice. notes 1 see terminology section. 2 temperature range: a, b version: ? 40 c to +105 c. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5303 (code 8 to 248); ad5313 (code 28 to 995); ad5323 (code 115 to 3981). 5 guaranteed by design and characterization, not production tested. 6 in order for the amplifier output to reach its minimum voltage, offset error must be negative. in order for the amplifier outpu t to reach its maximum voltage, v ref = v dd and offset plus gain error must be positive. specifications subject to change without notice.
rev. a e4e ad5303/ad5313/ad5323 i ol 2ma i oh 2ma c l 50pf to output pin 1.6v figure 1. load circuit for digital output (sdo) timing specifications sclk sync din * t 2 t 3 t 5 t 6 t 7 t 4 db15 t 1 db0 t 9 t 10 t 11 ldac ldac clr * see input shift register section t 8 figure 2. serial interface timing diagram
rev. a ad5303/ad5313/ad5323 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5303/ad5313/ad5323 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v digital input voltage to gnd . . . . . . . . ?.3 v to v dd + 0.3 v digital output voltage to gnd . . . . . . ?.3 v to v dd + 0.3 v reference input voltage to gnd . . . . . ?.3 v to v dd + 0.3 v v out a, v out b to gnd . . . . . . . . . . . . ?.3 v to v dd + 0.3 v operating temperature range industrial (a, b version) . . . . . . . . . . . . . . ?0 c to +105 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c junction temperature (t j m ax) . . . . . . . . . . . . . . . . . . 150 c 16-lead tssop package power dissipation . . . . . . . . . . . . . . . . . . . (t j m ax ?t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 160 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 clr ldac v dd v ref b v ref a v out a buf a buf b sdo gnd din sclk sync v out b pd dcen ad5303/ ad5313/ ad5323 ordering guide model temperature range package description package option AD5303ARU ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 AD5303ARU-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5313aru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5313aru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5323aru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5323aru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5303bru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5303bru-reel ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5303bru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5313bru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5313bru-reel ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5313bru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5323bru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5323bru-reel ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5323bru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16
rev. a e6e ad5303/ad5313/ad5323 pin function descriptions pin no. mnemonic function 1 clr active low control input that loads all zeros to both input and dac registers. 2 ldac active low control input that transfers the contents of the input registers to their respective dac registers. pulsing this pin low allows either or both dac registers to be updated if the input registers have new data. this allows simultaneous update of both dac outputs 3v dd power supply input. these parts can be operated from 2.5 v to 5.5 v, and the supply should be decoupled to gnd. 4v ref br eference input pin for dac b. this is the reference for dac b. it may be configured as a buffered or an unbuffered input, depending on the state of the buf b pin. it has an input range from 0 v to v dd in unbuf fered mode and from 1 v to v dd in buffered mode. 5v ref ar eference input pin for dac a. this is the reference for dac a. it may be configured as a buffered or an unbuffered input depending on the state of the buf a pin. it has an input range from 0 to v dd in unbuffered mode and from 1 v to v dd in buffered mode. 6v out ab uffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 7 buf a control pin that controls whether the reference input for dac a is unbuffered or buffered. if this pin is tied low, the reference input is unbuffered. if it is tied high, the reference input is buffered. 8 buf b control pin that controls whether the reference input for dac b is unbuffered or buffered. if this pin is tied low, the reference input is unbuffered. if it is tied high, the reference input is buffered. 9 dcen this pin is used to enable the daisy-chaining option. this should be tied high if the part is being used in a daisy-chain. the pin should be tied low if it is being used in standalone mode. 10 pd active low control input that acts as a hardware power-down option. this pin overrides any software power-down option. both dacs go into power-down mode when this pin is tied low. the dac outputs go into a high impedance state and the current consumption of the part drops to 200 na @ 5 v (50 na @ 3 v). 11 v out bb uffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 12 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the following 16 clocks. if sync is taken high before the 16th falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 13 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. the sclk input buffer is powered down after each write cycle. 14 din serial data input. this device has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. the din input buffer is powered down after each write cycle. 15 gnd ground reference point for all circuitry on the part. 16 sd o serial data output. can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. the serial data output is valid on the falling edge of the clock. terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the actual endpoints of the dac transfer function. a typical inl versus code plot can be seen in tpc 1. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl versus code plot can be seen in tpc 4. offset error this is a measure of the offset error of the dac and the output amplifier. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c.
rev. a ad5303/ad5313/ad5323 e7e major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac regis- ter changes state. it is normally specified as the area of the glitch in nv-secs and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device, but is measured when the dac is not being written to ( sync held high). it is specified in nv-secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of the other dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-secs. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of the other dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac low and monitoring the output of the other dac. the area of the glitch is expressed in nv-secs. dc crosstalk this is the dc change in the output level of one dac in re sponse to a change in the output of the other dac. it is measured with a full-scale output change on one dac while monitoring the other dac. it is expressed in v. power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is mea- sured in db. v ref is held at 2 v and v dd is varied 10%. reference feedthrough this is the ratio of the amplitude of the signal at the dac out- put to the reference input when the dac output is not being updated (i.e., ldac is high). it is expressed in db. total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference f or the dac and the thd is a measure of the harmonics present on the dac output. it is measured in db. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at w hich the output amplitude falls to 3 db below the input. channel-to-channel isolation this is a ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of the other dac. it is measured in db. gain error plus offset error output voltage negative offset error dac code negative offset error amplifier footroom (1mv) deadband ideal actual figure 3. transfer function with negative offset output voltage positive offset error dac code gain error plus offset error ideal actual figure 4. transfer function with positive offset
rev. a e8e ad5303/ad5313/ad5323etypical performance characteristics code inl error (lsb) 1.0 0.5 e1.0 050 250 100 150 200 0 e0.5 t a = 25 c v dd = 5v tpc 1. ad5303 typical inl plot code dnl error (lsb) 0.3 e0.3 050 250 100 150 200 e0.1 e0.2 0.2 0.1 0 t a = 25 c v dd = 5v tpc 4. ad5303 typical dnl plot v ref (v) 1.00 e1.00 0.25 0 0.75 0.50 error (lsb) 2345 e0.25 e0.50 e0.75 v dd = 5v t a = 25 c max inl max dnl min dnl min inl tpc 7. ad5303 inl and dnl error vs. v ref code inl error (lsb) 3 0 200 1000 400 600 800 0 e1 e2 e3 2 1 t a = 25 c v dd = 5v tpc 2. ad5313 typical inl plot 0.6 0.4 e0.2 e0.6 0.2 e0.4 code dnl error (lsb) 0 200 1000 400 600 800 0 t a = 25 c v dd = 5v tpc 5. ad5313 typical dnl plot temperature ( c) error (lsb) 1.00 0.75 e1.00 e40 0 120 40 80 0 e0.25 e0.50 e0.75 0.50 0.25 v dd = 5v v ref = 3v max inl max dnl min dnl min inl tpc 8. ad5303 inl error and dnl error vs. temperature code inl error (lsb) 12 0 1000 4000 2000 3000 0 e4 e8 e12 8 4 t a = 25 c v dd = 5v tpc 3. ad5323 typical inl plot code dnl error (lsb) 1.0 0.5 e1.0 0 1000 4000 2000 3000 0 e0.5 t a = 25 c v dd = 5v tpc 6. ad5323 typical dnl plot temperature ( c) error (%) e40 0 120 40 80 0.0 e0.5 e1.0 1.0 0.5 v dd = 5v v ref = 2v gain error offset error tpc 9. offset error and gain error vs. temperature
rev. a ad5303/ad5313/ad5323 e9e i dd ( a) frequency 0 100 150 400 200 250 350 300 v dd = 5v v dd = 3v tpc 10. i dd histogram with v dd = 3 v and v dd = 5 v v dd (v) i dd ( a) 600 0 2.5 3.0 5.5 3.5 4.0 300 200 100 500 4.5 5.0 both dacs in gain-of-two mode reference inputs buffered 400 e40 c +25 c +105 c tpc 13. supply current vs. supply voltage ch1 1v, ch2 5v, time base = 5 s/div ch2 ch1 clk v out v dd = 5v t a = 25 c tpc 16. half-scale settling (1/4 to 3/4 scale code change) sink/source current (ma) v out (v) 5 0 01 23 3 2 1 4 45 6 5v source 3v source 3v sink 5v sink tpc 11. source and sink current capability v dd (v) 1.0 0.9 0 2.7 3.2 5.2 3.7 4.2 4.7 0.4 0.3 0.2 0.1 0.8 0.6 0.7 0.5 both dacs in three-state condition e40 c +25 c +105 c i dd ( a) tpc 14. power-down current vs. supply voltage ch1 1v, ch2 1v, time base = 20 s/div ch2 ch1 v dd v out a t a = 25 c tpc 17. power-on reset to 0 v i dd ( a) 600 0 zero scale full scale 200 100 500 400 300 v dd = 5v t a = 25 c tpc 12. supply current vs. code v logic (v) 700 100 0 0.5 4.5 1.5 2.5 3.5 400 300 600 500 i dd ( a) 1.0 2.0 3.0 4.0 5.0 200 t a = 25 c v dd = 5v v dd = 3v tpc 15. supply current vs. logic input voltage ch1 1v, ch3 5v, time base = 1 s/div ch3 ch1 clk t a = 25 c tpc 18. exiting power-down to midscale
rev. a e10e ad5303/ad5313/ad5323 1 s /div 2.48 2.49 v out (v) 2.47 2.50 tpc 19. ad5323 major-code transition v ref (v) 0.10 e0.10 0.00 0.05 full-scale error (v) 12345 e0.05 v dd = 5v t a = 25 c 0 tpc 22. full-scale error vs. v ref (buffered) frequency (hz) 10 e40 e20 e30 0 e10 db 10 100 100k 10k e50 e60 1k 1m 10m tpc 20. multiplying bandwidth (small-signal frequency response) 500ns/div 2mv/div tpc 21. dac-dac crosstalk
rev. a ad5303/ad5313/ad5323 e11e functional description the ad5303/ad5313/ad5323 are dual resistor-string dacs fabricated on a cmos process with resolutions of 8, 10 and 12 bits respectively. they contain reference buffers and output buffer amplifiers, and are written to via a 3-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/ s. each dac is provided with a separate reference input, which may be buffered to draw virtually no current from the reference source, or unbuffered to give a refer- ence input range from gnd to v dd . the devices have three programmable power-down modes, in which one or both dacs may be turned off completely with a high impedance output, or the output may be pulled low by an on-chip resistor. digital-to-analog section the architecture of one dac channel consists of a reference buffer and a resistor-string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the dac. figure 5 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by v vd out ref n = 2 where d = decimal equivalent of the binary code, which is loaded to the dac register: 0 ? 255 for ad5303 (8 bits) 0 ? 1023 for ad5313 (10 bits) 0 ? 4095 for ad5323 (12 bits) n = dac resolution resistor string output buffer amplifier input register dac register buf a reference buffer v out a v ref a figure 5. single dac channel architecture resistor string the resistor string section is shown in figure 6. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier figure 6. resistor string dac reference inputs there is a reference input pin for each of the two dacs. the reference inputs are buffered but can also be configured as unbuffered. the advantage with the buffered input is the high impedance it presents to the voltage source driving it. however, if the unbuffered mode is used, the user can have a reference voltage as low as gnd and as high as v dd since there is no restriction due to headroom and footroom of the reference amplifier. if there is a buffered reference in the circuit (e.g., ref192), there is no need to use the on-chip buffers of the ad5303/ ad5313/ad 5323. in unbuffered mode, the input impedance is still large at typically 180 k per reference input for 0 v to v ref mode and 90 k for 0 v to 2 v ref mode. the buffered/unbuffered option is controlled by the buf a and buf b pins. if the buf pin is tied high, the reference input is buffered, if tied low, it is unbuffered. output amplifier the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail, which gives an output range of 0.001 v to v dd ? 0.001 v when the reference is v dd . it is capable of driving a load of 2 k in parallel with 500 pf to gnd and v dd . the source and sink capabilities of the output amplifier can be seen in tpc 11. the slew rate is 0.7 v/ s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s. power-on reset the ad5303/ad5313/ad5323 are provided with a power-on reset function, so that they power up in a defined state. the power-on state is ? normal operation ? 0 v to v ref output range ? output voltage set to 0 v both input and dac registers are filled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. clear function ( clr clr c
rev. a e12e ad5303/ad5313/ad5323 serial interface the ad5303/ad5313/ad5323 are controlled over a versatile, 3-wire serial interface, which operates at clock rates up to 30 mhz and is compatible with spi, qspi, microwire, and dsp interface standards. input shift register the input shift register is 16 bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this operation is shown in figure 2. the 16-bit word consists of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. the first bit loaded is the msb (bit 15), which determines whether the data is for dac a or dac b. bit 14 determines the output range (0 v to v ref or 0 v to 2 v ref ). bits 13 and 12 control the operating mode of the dac. table i. control bits power-on bit name function default 15 a /b 0: data written to dac a n/a 1: data written to dac b 14 gain 0: output range of 0 v to v ref 0 1: output range of 0 v to 2 v ref 13 pd1 mode bit 0 12 pd0 mode bit 0 the remaining bits are dac data bits, starting with the msb and ending with the lsb. the ad5323 uses all 12 bits of dac data, the ad5313 uses 10 bits and ignores the 2 lsb. the ad5303 uses eight bits and ignores the last four bits. the data format is straight binary, with all 0s corresponding to 0 v output, and all 1s corresponding to full-scale output (v ref ? 1 lsb). the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can be trans ferred into the device only while sync is low. to start the serial data transfer, sync should be taken low observing the mini- mum sync to sclk active edge setup time, t 4 . after sync goes low, serial data will be shifted into the device ? s input shift register on the falling edges of sclk for 16 clock pulses. any data and clock pulses after the 16th will be ignored, and no further serial data transfer will occur until sync is taken high and low again. sync may be taken high after the falling edge of the 16th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected dac. if sync is taken high before the 16th falling edge of sclk, the data transfer will be aborted and the input registers will not be updated. when data has been transferred into both input registers, the dac registers of both dacs may be simultaneously updated, by taking ldac low. clr is an active-low, asynchronous clear that clears the input and dac registers of both dacs to all 0s. low power serial interface to reduce the power consumption of the device even further, the interface only powers up fully when the device is being writ- ten to. as soon as the 16-bit control word has been written to the part, the sclk and din input buffers are powered down. they only power up again following a falling edge of sync . double-buffered interface the ad5303/ad5313/ad5323 dacs all have double-buff- ered interfaces consisting of two banks of registers ? input registers and dac registers. the input register is connected directly to the input shift register and the digital code is trans- ferred to the relevant input register on completion of a valid write sequence. the dac register contains the digital code used by the resistor string. access to the dac register is controlled by the ldac function. when ldac is high, the dac register is latched and the input register may change state without affecting the contents of the dac register. however, when ldac is brought low, the dac register becomes transparent and the contents of the input regis- ter are transferred to it. this is useful if the user requires simultaneous updating of both dac outputs. the user may write to both input registers indi- vidually and then, by pulsing the ldac input low, both outputs will update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the a /b gain pd1 pd0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x db0 (lsb) db15 (msb) data bits figure 7. ad5303 input shift register contents a /b gain pd1 pd0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x db0 (lsb) db15 (msb) data bits figure 8. ad5313 input shift register contents a /b gain pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db0 (lsb) db15 (msb) data bits figure 9. ad5323 input shift register contents
rev. a ad5303/ad5313/ad5323 e13e contents of the input registers. in the case of the ad5303/ad5313/ ad5323, the part will only update the dac register if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down modes the ad5303/ad5313/ad5323 have very low power con sump- tion, dissipating only 0.7 mw with a 3 v supply and 1.5 mw with a 5 v supply. power consumption can be further re duced when the dacs are not in use by putting them into one of three power-down modes, which are selected by bits 13 and 12 (pd1 and pd0) of the control word. table ii shows how the state of the bits corresponds to the mode of operation of that particular dac. table ii. pd1/pd0 operating modes pd1 pd0 operating mode 00 normal operation 01 power-down (1 k load to gnd) 10 power-down (100 k load to gnd) 11 power-down (high impedance output) when both bits are set to 0, the dacs work normally with their normal power consumption of 300 a at 5 v. however, for the three power-down modes, the supply current falls to 200 na at 5 v (50 na at 3 v) when both dacs are powered down. not only does the supply current drop but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. there are three different options. the output is connected internally to gnd through either a 1 k resistor or a 100 k resistor, or it is left in a high impedance state (three-state). the output stage is illus- trated in figure 10. the bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. see tpc 18 for a plot. the software power-down modes programmed by pd0 and pd1 are overridden by the pd pin. taking this pin low puts both dacs into power-down mode simultaneously and both outputs are put into a high impedance state. if pd is not used, it should be tied high. amplifier power-down circuitry resistor network resistor string dac v out figure 10. output stage during power-down microprocessor interfacing ad5303/ad5313/ad5323 to adsp-2101/adsp-2103 interface figure 11 shows a serial interface between the ad5303/ad5313/ ad5323 and the adsp-2101/adsp-2103. the adsp-2101/ adsp-2103 should be set up to operate in the sport trans- mit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active-low framing, 16-bit word length. transmission is initi- ated by writing a word to the tx register after the sport has been enabled. sclk din sync tfs dt sclk adsp-2101/ adsp-2103 * * additional pins omitted for clarity. ad5303/ ad5313/ ad5323 * figure 11. ad5303/ad5313/ad5323 to adsp-2101/ adsp-2103 interface ad5303/ad5313/ad5323 to 68hc11/68l11 interface figure 12 shows a serial interface between the ad5303/ad5313/ ad5323 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5303/ad5313/ ad5323, while the mosi output drives the serial data line (din) of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be config- ured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data to the ad5303/ad5313/ad5323, pc7 is left low after the first eight bits are transferred and a second serial write operation is performed to the dac; pc7 is taken high at the end of this procedure. din sclk sync pc7 sck mosi 68hc11/68l11 * * additional pins omitted for clarity. ad5303/ ad5313/ ad5323 * figure 12. ad5303/ad5313/ad5323 to 68hc11/ 68l11 interface
rev. a e14e ad5303/ad5313/ad5323 ad5303/ad5313/ad5323 to 80c51/80l51 interface figure 13 shows a serial interface between the ad5303/ad5313/ ad5323 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5303/ad5313/ad5323, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5303/ad5313/ ad5323, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in a format that has the lsb first. the ad5303/ad5313/ ad5323 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. din sclk sync p3.3 txd rxd 80c51/80l51 * * additional pins omitted for clarity. ad5303/ ad5313/ ad5323 * figure 13. ad5303/ad5313/ad5323 to 80c51/ 80l51 interface ad5303/ad5313/ad5323 to microwire interface figure 14 shows an interface between the ad5303/ad5313/ ad5323 and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5303/ad5313/ad5323 on the rising edge of the sk. din sclk sync cs sk so microwire * * additional pins omitted for clarity. ad5303/ ad5313/ ad5323 * figure 14. ad5303/ad5313/ad5323 to microwire interface applications information typical application circuit the ad5303/ad5313/ad5323 can be used with a wide range of reference voltages, especially if the reference inputs are con- figured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, the ad5303/ad5313/ad5323 may be used with a fixed precision reference voltage. figure 15 shows a typical setup for the ad5303/ad5313/ad5323 when using an external reference. if the reference inputs are unbuffered, the reference input range is from 0 v to v dd , but if the on-chip reference buffers are used, the reference range is reduced. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ref191, a 2.048 v reference. 1 f v ref a v ref b sclk din sync v dd gnd v out a v out b v dd = 2.5v to 5.5v v out ext ref ad780/ref192 with v dd = 5v or ref191 with v dd = 2.5v serial interface buf a buf b ad5303/ ad5313/ ad5323 figure 15. ad5303/ad5313/ad5323 using external reference if an output range of 0 v to v dd is required when the reference inputs are configured as unbuffered (for example 0 v to 5 v), the simplest solution is to connect the reference inputs to v dd . as th is supply may not be very accurate and may be noisy, the ad5303/ad5313/ad5323 may be powered from the reference voltage, for example using a 5 v reference such as the ref195, as shown in figure 16. the ref195 will output a steady supply voltage for the ad5303/ad5313/ad5323. the current required from the ref195 is 300 a supply current and approximately 30 a or 60 a into each of the reference inputs (if unbuffered). this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k load on each output) is: avk ma + () = /. the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 2.7 ppm (13.5 v) for the 1.36 ma current drawn from it. this corresponds to a 0.0007 lsb error at eight bits and 0.011 lsb error at 12 bits. 1 f v ref a v ref b v dd 15v v out v in gnd ref195 0.1 f 10 f sclk din sync serial interface gnd v out a v out b buf a buf b ad5303/ ad5313/ ad5323 figure 16. using an ref195 as power and reference to the ad5303/ad5313/ad5323
rev. a ad5303/ad5313/ad5323 e15e bipolar operation using the ad5303/ad5313/ad5323 the ad5303/ad5313/ad5323 has been designed for single- supply operation, but bipolar operation is also achievable using the circuit shown in figure 17. the circuit shown has been config- ured to achieve an output voltage range of ? 5v < v out < +5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or op295 as the output amplifier. 1 f v ref a/b v dd v out a/b 0.1 f 10 f v dd = +5v ad820/ op295 5v +5v r1 10k r2 10k sclk din sync gnd serial interface buf a buf b ad5303/ ad5313/ ad5323 v out v in gnd ref195 e5v +6v to +16v figure 17. bipolar operation using the ad5303/ ad5313/ad5323 the output voltage for any input code can be calculated as follows: vvd rrrvrr out ref n ref = () () + () () [] // ? / 2121 21 where d is the decimal equivalent of the code loaded to the dac and n is the dac resolution. v ref is the reference voltage input, and gain bit = 0. with v ref = 5 v r 1 = r 2 = 10 k and v dd = 5 v: vdv out n = () 10 2 5 / ? opto-isolated interface for process control applications the ad5303/ad5313/ad5323 has a versatile 3-wire serial interface making it ideal for generating accurate voltages in process control and industrial applications. due to noise, safety requirements, or distance, it may be necessary to isolate the ad5303/ad5313/ad5323 from the controller. this can easily be achieved by using opto-isolators, which will provide isolation in excess of 3 kv. the serial loading structure of the ad5303/ ad5313/ad5323 makes it ideally suited for use in opto-isolated applications. figure 18 shows an opto-isolated interface to the ad5303/ad5313/ad5323 where din, sclk, and sync are driven from opto-couplers. the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5303/ad5313/ad5323. v dd sclk 10k v ref a din sync v dd gnd v out a 0.1 f 10 f buf a buf b v ref b v out b sclk 5v regulator power v dd sync 10k v dd din 10k ad5303/ ad5313/ ad5323 figure 18. ad5303/ad5313/ad5323 in an opto- isolated interface decoding multiple ad5303/ad5313/ad5323s the sync pin on the ad5303/ad5313/ad5323 can be used in applications to decode a number of dacs. in this application, all the dacs in the system receive the same serial clock and serial data, but only the sync to one of the devices will be active at any one time, allowing access to two channels in this 8-channel system. the 74hc139 is used as a 2-to-4 line decoder to address any of the dacs in the system. to prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 19 shows a diagram of a typical setup for decoding multiple ad5303/ad5313/ad5323 devices in a system. 74hc139 v cc v dd enable coded address 1g 1a 1b dgnd sync din sclk 1y0 1y1 1y2 1y3 sync din sclk sync din sclk sync din sclk sclk din ad5303/ ad5313/ ad5323 ad5303/ ad5313/ ad5323 ad5303/ ad5313/ ad5323 ad5303/ ad5313/ ad5323 figure 19. decoding multiple ad5303/ad5313/ ad5323 devices in a system
rev. a e16e ad5303/ad5313/ad5323 ad5303/ad5313/ad5323 as a digitally programmable wi n dow detector a digitally programmable upper/lower limit detector using the two dacs in the ad5303/ad5313/ad5323 is shown in figure 20. the upper and lower limits for the test are loaded to dacs a and b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led will indicate the fail condition. v ref a v ref b sclk din sync v dd gnd v out a v out b 5v 0.1 f 10 f sclk din sync v ref v in 1/2 cmp04 1k fail pass/ fail 1k pass 1/6 74hc05 ad5303/ ad5313/ ad5323 figure 20. window detector using ad5303/ ad5313/ad5323 coarse and fine adjustment using the ad5303/ad5313/ad5323 the dacs in the ad5303/ad5313/ad5323 can be paired together to form a coarse and fine adjustment function, as shown in figure 21. dac a is used to provide the coarse adjustment while dac b provides the fine adjustment. varying the ratio of r1 and r2 will change the relative effect of the coarse and fine adjustments. with the resistor values and external reference shown, the output amplifier has unity gain for the dac a output, so the output range is 0 v to 2.5 v ? 1 lsb. for dac b, the amplifier has a gain of 7.6 10 ? 3 , giving dac b a range equal to 19 mv. the circuit is shown with a 2.5 v reference, but reference voltages up to v dd may be used. the op amps indicated will allow a rail- to-rail output swing. 1 f v ref a v dd gnd v out b 0.1 f 10 f v dd = 5v v out v in gnd ext ref ad820/ op295 +5v r3 51.2k r4 390 ad780/ref192 with v dd = 5v v out a v ref b r1 390 r2 51.2k v out ad5303/ ad5313/ ad5323 figure 21. coarse/fine adjustment daisy-chain mode this mode is used for updating serially connected or stand alone devices on the rising edge of sync . for systems that contain several dacs, or where the user wishes to read back the dac contents for diagnostic purposes, the sdo pin may be used to daisy-chain several devices together and provide serial readback. by connecting the dcen (daisy-chain enable) pin high, the daisy-chain mode is enabled. it is tied low in the case of standa- lone mode. in daisy-chain mode the internal gating on sclk is disabled. the sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out after the falling edge of sclk and is valid on the subsequent rising and falling edges. by connecting this line to the din input on the next dac in the chain, a multidac interface is constructed. sixteen clock pulses are required for each dac in the system. therefore, the total number of clock cycles must equal 16n, where n is the total number of devices in the chain. when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data being clocked into the input shift register. a continuous sclk source may be used if it can be arranged that sync is held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles may be used and sync may be taken high some time later. when the transfer to all input registers is complete, a common ldac signal updates all dac registers and all analog outputs are updated simultaneously. 68hc11 * miso sync din sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo din din * additional pins omitted for clarity ad5303/ ad5313/ ad5323 * (dac 1) ad5303/ ad5313/ ad5323 * (dac 2) ad5303/ ad5313/ ad5323 * (dac n) figure 22. daisy-chain mode
rev. a ad5303/ad5313/ad5323 e17e sclk sync din t 2 t 3 t 5 t 6 t 4 t 1 t 14 db15 db0 db15 db0 db15 db0 sdo input word for dac n input word for dac (n+1) undefined input word for dac n sclk sdo t 13 t 12 v il v ih t 8 t 15 figure 23. daisy-chaining timing diagram power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5303/ad5313/ad5323 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5303/ad5313/ad5323 is in a system where multiple devices require an agnd to dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the ad5303/ad5313/ad5323. the ad5303/ad5313/ad5323 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5303/ad5313/ad5323 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. a ?8 ad5303/ad5313/ad5323 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab
rev. a ad5303/ad5313/ad5323 e19e revision history location page 8/03?data sheet changed from rev. 0 to rev. a. added a version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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